1. Field of the Invention
The present invention relates to a statistic counter device, and in particular to a statistic counter device comprising a plurality of statistic counters which count statistic information.
Together with a recent speed enhancement in a communication technology and spread of a device therefor such as a mobile telephone and the Internet, kinds and number of statistic information such as kinds and number of packets have been increased more and more. In order to deal with such statistic information, it is required to increase the number of statistic counters and the bit number thereof.
2. Description of the Related Art
FIG. 12 shows a router (or router board) 200z connected to a network 400. The router 200z is provided with a routing chip 110z, physical layer interfaces 150_1 and 150_2, MAC layer interfaces 140_1 and 140_2, a CPU 130 and a memory 120.
The routing chip 110z is provided with 32-bit statistic counters 10z_1-10z_65536 (hereinafter, occasionally represented by a reference numeral 10z), and the memory 120 is provided with e.g. 48-bit packet counters 121_1-121_65536 (hereinafter, occasionally represented by a reference numeral 121) respectively corresponding to the statistic counters 10z_1-10z_65536.
The statistic counter 10z is (1) for counting transmission/reception packets, (2) for counting discarded packets or (3) for an octet counter.
The statistic counter for the transmission/reception packets in the above-mentioned (1) is used for billing, a fault investigation and the like, the statistic counter for discarded packets in the above-mentioned (2) is used for the fault investigation and the like, and the octet counter in the above-mentioned (3) is used for a bandwidth management, the billing, the fault investigation and the like.
By taking the statistic counter 10z counting the packets in the above-mentioned (1) and (2) as an example, operations related to the statistic counter 10z will now be described. The bit number of the statistic counter 10z is 32 bits in the same way as that for general data or the like.
Step T51: A statistic counter device 100z receives packets P1 through the physical layer interface 150_1 and the MAC layer interface 140_1 from the network 400. The statistic counter 10z_1 corresponding to the packets P1 in the statistic counter device 100z counts the packets P1 from a corresponding user.
Then, the packets P1 are transmitted to the network 400 through the MAC layer interface 140_2 and the physical layer interface 150_2.
Hereafter, packets P2-P65536 from users of the network 400 are similarly counted by the corresponding statistic counters 10z_2-10z_65536, respectively.
Steps T52 and T53: The 32-bit statistic counter 10z_1 can not count the packets P1 equal to or more than “232-1” (≈4,000,000,000). Therefore, before all of the bits of the statistic counter 10z_1 assume “1”, for example, the CPU 130 reads the value of the statistic counter 10z_1, adds the value to the packet counter 121_1 in the memory 120, and resets the statistic counter 10z_1 to “0”.
Similarly, before all of the bits of the statistic counters 10z_2-10z_65536 assume “1” respectively, the CPU 130 reads the values of the statistic counters 10z_2-10z_65536, adds the values to the packet counters 121_2-121_65536, and resets the statistic counters 10z_2-10z_65536 to “0”.
Thus, it becomes possible to count e.g. the packets P1 until the packet counter 121_1 reaches a full count based on the bit number. If the bit number of e.g. the packet counter 121_1=“48”, the packets up to “248-1” can be counted.
When the router 200z has numerous communication lines such as Internet Data Center (hereinafter, abbreviated as IDC), counting process per user is required, so that the number of counters increases. Also, with a speed enhancement (10 Mbps→100 Mbps→1 Gbps→10 Gbps) of a communication line speed, a packet flow per unit time increases, so that it is required to increase the bit number of the counter which counts the packet flow.
When a communication line bandwidth is 10 Gbps, for example, the packet flow per second assumes approximately 15 Mpps (1 packet=64 bytes). Supposing that an access period of the CPU 130 requires approximately four minutes, the count of the statistic counter 10z for four minutes assumes 15 Mpps*4*60≈3.6 G<232, namely the required bit number of each statistic counter 10z assumes 32 bits.
As a result, enlarging the hardware scale and increasing the power consumption become significant problems.
The maximum capacity of a chip composing the statistic counter device 100z is approximately 17 MBC (Basic Cell) in case of 14 mm □ chip of 0.11 μm process. The counter scale is approximately 1.4 kBC in the 32-bit counter, and 3.5 kBC in the 36-bit counter.
When the statistic counter counts packets of only a single kind for 1000 users, for example, a percentage of the statistic counter to the entire chip assumes approximately 8% (≈(1.4 k×1000/17 M)×100) in the 32-bit counter, so that the scale of the statistic counter in the entire chip is too large to be neglected. Also, the percentage of the power consumption of the statistic counter to the entire chip assumes substantially the same percentage as the statistic counter scale.
As an example of a counter reducing a total bit number of two counters (e.g. X/Y address counters respectively counting addresses in the directions of X and Y), there is a single counter in which a first counting means (lower digit side), a second counting means of “n” (“n” is a positive integer) units, and a third counting means (higher digit side) are cascaded (see e.g. patent document 1).
This counter is separated into two counters, which are respectively made an X address counter and a Y address counter. Namely, the X address counter is composed of the first counting means and a second counting means of 0−i (i≦n) units of lower digit side, and the Y address counter is composed of the second counting means of the remaining higher digit side and the third counting means, whereby bit numbers of the X address counter and the Y address counter are made variable to reduce the hardware scale.
A first counting circuit uses a counter of a fixed bit number in this device. Therefore, when a user who can use a counter with a smaller bit number than the fixed bit number uses the first counting circuit, there has been a disadvantage of incurring waste in the hardware.
As a counting circuit (counter) for improving the disadvantage, there is a counting circuit including a predetermined number of unit counters performing a calculation operation in response to supplies of a start bit selection signal designating either a carry output of a counter at a preceding stage or a predetermined voltage level to be effective as a carry input and a count enable signal designating a count operation permission/prohibition, outputting a predetermined count result and outputting a carry output to a subsequent stage to be cascaded, and the predetermined number of registers temporarily storing the start bit selection signal and the count enable signal and outputting the start bit selection signal and the count enable signal to each of the unit counters (see e.g. patent document 2).
Since this counting circuit can be divided into a plurality of independent counters of arbitrary bit numbers, hardware resources can be efficiently used flexibly meeting with user's request.
However, in the above-mentioned two methods, the bit number of each counter has to be preliminarily designated and the optimum bit number can not be automatically designated during the count operation.    <Patent Document 1>
Japanese Patent Application Laid-open No. 4-227582    <Patent Document 2>
Japanese Patent Application Laid-open No. 8-237112